The present invention relates to a method and apparatus for data transfer between a bus master and a bus slave in a computer system, wherein the bus master is a central processing unit (hereinafter referred to as "CPU"), an input/output device (hereinafter referred to as "I/O device") or the like, and the bus slave is a memory or the like.
In the prior art, for example, as shown in Japanese patent application laid-open No. 61-234450 "Processor", since the timing of the negation of the data confirmation signal of the immediately preceding data transfer cycle is performed within a predetermined time specified as electric characteristics, the timing of the assertion of the data strobe signal is set to be delayed after the predetermined time.
In the hand shake system of the prior art, negation of the data confirmation ACK signal is performed within a predetermined time specified as electric characteristics after the data strobe signal DSS is negated indicated by arrow 20 in FIGS. 2A-2B, and the next data transfer is started by the strobe signal being asserted after the above-mentioned predetermined time. Most of the predetermined time is proportional to the product of the load capacitance C of the data confirmation signal line and the pull-up resistance R, and since the load capacitance C is varied as the connection number of the bus slave is increased or decreased, the predetermined time must be estimated to maximum value and the upper limit of the data transfer speed is specified.
That is, in the structure of the prior art, the bus master asserts the data strobe signal DSS at the data transfer starting time and informs the bus slave of it. The bus slave asserts the data confirmation signal ACK after the data transmission to the data bus at the data read state and after the receiving of data from the data bus at the data write state, and informs the bus master of it. The bus master negates the data strobe signal DSS after the receiving of data from the data bus at the data read state and after the outputting of the data to the data bus at the data write state. The bus slave detects that the data strobe signal DSS is negated, and stops the output of data to the data bus at the data read state and also negates the data confirmation signal ACK indicating the data transfer of one time is finished. In this case, since the data confirmation signal ACK is driven so that it does not collide with signals of a plurality of bus slaves, the signal line of the ACK is constructed with a three-state driver and connected to a pull-up resistance.
In this construction, after the data strobe signal DSS is negated, the timing chart of negation of the data confirmation signal ACK is shown in FIG. 2B. The time spent after the negation of the bus slave until the data confirmation signal ACK exceeds a threshold voltage is proportional to the product of the load capacitance C of the data confirmation signal ACK and the pull-up resistance R, and the load capacitance C is varied as the number of bus slaves connected to the ACK signal line is increased.
In fact, when R=3. 8 k ohms and C=100 pF, the time becomes about 200 nS, and when C=200 pF, it becomes about 400 nS. In this case, if the data strobe signal for a next data transfer is asserted before the data confirmation signal ACK exceeds the threshold voltage, error operation will be produced. In other words, the data strobe signal DSS is not to be asserted before the data confirmation signal exceeds the threshold value as indicated by arrow 22 in FIGS. 2A-2B. Consequently, in the construction of the prior art, the assertion timing of the data strobe signal must be sufficiently delayed. As a result, the data transfer speed cannot be increased.